Project EOGee: EOGee2 and DC Coupling, Part 3

The main barrier to getting a DC coupled signal using EOGee1 was that the DC offset voltage of the EOGee signal was much larger than the actual signal itself. Because the signal itself is so small we need a large gain to amplify it, but this also amplifies the offset voltage which then saturates the amplifier.

My solution is to use a signal chain like this:

sigchain

EOGee2 Signal Chain

Firstly the input has three voltage components – a common mode component, the drift component and the EOG signal itself from the corneo-retinal potential (CRP). The common mode is removed by the differential amplifier of the first stage. This then amplifies both the EOG signal and the drift by a factor of G1.

We need to ensure at this point that the amplifier is not saturated, so we have to ensure that in the worst case the output voltage V1 is less than our 3.3V rail. I don’t have a lot of data on exactly how large the drift component can be but I’ve never seen it higher than +/-20mV so I will choose that as an upper limit. From literature, the EOG signal tends to be less than +/-1mV. Therefore we must keep our first stage gain less than 78.6 (21mV * 78.6 = 1.65V). A gain of G1=66.87 allows an easy component choice and also gives some margin.

This amplified signal is then fed into a summing node where we subtract a voltage reference from it. This voltage reference is generated by a DAC in the microcontroller which allows us to dynamically adjust the reference voltage to cancel out the drift component and ensure that the output, V2, is centred around 1.65V. We are using a 12-bit DAC which means that our step size is about 0.8mV. This means that we can cancel out the drift to within about 0.4mV. Therefore V2 is equal to the EOG signal multiplied by the gain of the first stage plus our cancellation error, which is at maximum 67.27mV (=1mV * 66.87 + 0.4mV).

Screenshot 2020-04-22 at 23.20.05

The first gain stage and the offset stage are achieved with the AD8226

Our second gain stage should amplify V2 up to the full 3.3V range. Therefore our gain must be less than 24.5 to prevent saturation. In EOGee1, the second gain stage had a gain of 220, in this case we can just swap a 10kΩ resistor for a 100kΩ resistor to get a gain of 22.

Screenshot 2020-04-22 at 23.21.29

The second gain stage also has a 560pF capacitor to set create a 130Hz LPF

The final stage is a variable gain stage. We use an MCP41010 chip from Microchip which creates a variable resistance from 0Ω to 10kΩ, controllable over SPI. With this we can achieve a gain between 0.5 and 1.5 in order to adjust the signal as needed if the size of the EOG signal is too small or too large.

Screenshot 2020-04-22 at 23.22.26

The final gain stage is variable using an MCP41010

Now that we have the capability to cancel out the offset voltage, we need to write the firmware to do so.

The code has been modified so that if the ADC reading becomes too high or too low, the microcontroller will begin to adjust the DAC output appropriately until the signal level has been brought back down to 1.65V.

Screenshot 2020-04-18 at 19.36.25

The microcontroller recenters the signal by adjusting the DAC

This has been very successful and has been capable of cancelling out all drift that I have seen. Although the data during this correction transition is unusable, it is generally less than a second in length.

Now that I have the ability to DC couple the signal, the potential for this technique is becoming much more clear, as demonstrated in this video:

2 thoughts on “Project EOGee: EOGee2 and DC Coupling, Part 3

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out /  Change )

Google photo

You are commenting using your Google account. Log Out /  Change )

Twitter picture

You are commenting using your Twitter account. Log Out /  Change )

Facebook photo

You are commenting using your Facebook account. Log Out /  Change )

Connecting to %s