HP2VGA: PCB Design with a BGA

This PCB represents two firsts for me – first 4 layer board and first BGA package. The former isn’t really a big deal and is really just necessary because of the latter. Due to my memory requirements, I was forced to use the Lattice iCE40HX8k which has more RAM than the smaller variant, iCE40HX4k, and also only comes in BGA packages.

Screenshot from 2018-08-07 23-23-10

PCB design without floods

I decided to use OSHPark to manufacture the board because their pricing is very reasonable at $10 per square inch, and they were also capable of making small enough traces and vias to break out the 0.8mm pitch BGA package, unlike my usual vendor Seeed Studio. The only things I don’t really like about OSHPark are the little “mouse bites” you get all around your board and have to clean up yourself (see final image), and also I think that the purple silkscreen is unusual looking – although I understand the reasons that they went for this. One nice thing is the ENIG finish which will hopefully make soldering easier.

I wanted to minimise the PCB area to save money, although I’m starting to suspect I pushed a little hard and I won’t be able to fix any problems with bodges as everything is so small. Fingers crossed everything works.

I followed Xilinx’s Recommended Layout Dimensions document to choose a via and trace size for breaking out the PCB.

Screenshot from 2018-08-07 23-31-28.png

Image from “Recommended Design Rules and Strategies for BGA Devices” by Xilinx

The chip has multiple power pins and therefore needs multiple decoupling capacitors. To save space I put most passive components on the bottom of the board. To fit the capacitors between all of the vias I had to downsize to 0402 resistors instead of my usual 0603.

Screenshot from 2018-08-07 23-28-52.png

The 0402 capacitors just fit in between all of the vias. 0603 didn’t fit.

The board arrived today. I only have three so I best hope that the BGA soldering goes well.

IMG_2892

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2 thoughts on “HP2VGA: PCB Design with a BGA

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