Project: Nixie Clock (upgrade) – SPI Bus Chip Select/GPIO Contention

As discussed in the previous article, the display is controlled by a number of shift registers. Shift registers can be controlled directly by a SPI bus, which is useful as most microcontrollers (including our ATtiny87) have a built in SPI bus peripheral. This means that writing a byte to the shift register is almost as easy as just writing a byte to a register.

A SPI bus between two chips has four lines: MOSI (master to slave communication), MISO (slave to master communication), CLK (controlled by the master) and SS (line used to select the slave and begin communication, aka Chip Select).

When designing the board I was under the false impression that the SS line was entirely software controlled when operating as the master and therefore I could effectively use any pin I like. Therefore I put the SS line on a normal GPIO pin, and used the SS pin as the input for the switches (I don’t know why I chose to do this).

Unfortunately the datasheet now tells me this:

Screenshot from 2017-09-06 23-21-46.png

This means that when the user triggers the switch on the clock (perhaps trying to set the time) forcing the SS pin low, the SPI will stop behaving as a master and become a slave, thus breaking the display.

While I could technically get around this by setting the SS line as an output while performing any transmission to prevent the SPI being pulled out of master mode, it seems like a hassle that is likely to introduce bugs.

Instead I opted to bit-bang the SPI bus in software thus avoiding this issue. In general the main downside of this is that it requires to processor to focus on this task and prevents it going to sleep, rather than having the hardware peripheral handling the transfer in the background. In this case it’s not much of an issue as the processor doesn’t have much to do, and it’s barely worth going to sleep for such a short time.

Screenshot from 2017-09-06 23-38-22.png

Code to perform bit-banging of the SPI bus

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