After putting this project on the back burner, I am focusing on it once again. Brian HG on the EEVblog forums suggested that a simple line doubler would make the signal compatible with most modern VGA displays. What that means is that each line in the frame needs to be repeated twice, at double the speed.
Currently we get a new line every 40 microseconds, but this is too slow for most displays to be happy about. Therefore, if we record each line and output it twice at 20 microseconds each most VGA displays will be ok with it.
I wanted to verify this, so I used my Nexys 4 DDR FPGA board from Digilent to first simulate the video signals from my oscilloscope. As expected, I couldn’t find any monitors that would lock onto the signal. I then doubled the line frequency and found that every monitor I tried (Samsung, Acer, HP) locked onto it! So that tells me a simple line doubler will work.
The good thing about this is that I need only ever store one or two lines in memory. Assuming 640 pixels per line, at 3 bits each that is only about 4kBits of memory which is very feasible on a low end FPGA without external memory.
During development I expect to need access to the video signals in the oscilloscope. This would mean opening up my oscilloscope and disconnecting the display. On top of being messy, this would mean that I couldn’t use the oscilloscope to help me debug. My solution was to build an interposer board that sits between the display and the display cable.
This cable just connects the signals to the display, but also allows me to tap off the V-Sync, H-Sync, Video, +12V and GND signals. On top of this, I can actually use the oscilloscope to measure its own video signals!